Semiconductor integrated circuits wafers are produced by a plurality of processes in a wafer fabrication facility (fab). These processes, and associated fabrication tools, may include thermal oxidation, diffusion, ion implantation, RTP (rapid thermal processing), CVD (chemical vapor deposition), PVD (physical vapor deposition), epitaxy, etch, and photolithography. During the fabrication stages, products (e.g., semiconductor wafers) are monitored and controlled for quality and yield using metrology tools. As integrated circuits feature sizes are reduced, the amount of monitoring and controlling may need to be increased. This, however, increases costs by the increased quantity of metrology tools required, the increased manpower to perform the monitoring and controlling, and the associated delay in manufacturing cycle time.
Accordingly, a virtual metrology model is utilized for the production control and other purposes with reduced cost. However, the existing virtual metrology model is designed for and can only predict wafer result for single wafer processing tools. A batch of wafers processed in a batch processing tool cannot be properly predicted for their wafer results. For example, a thermal processing chamber may include a vertical furnace to hold and process a batch of wafers positioned in various vertical positions. Usually, the furnace has a thermal field depending on the location of the vertical level. Each of the batch wafers in the batch processing tool may experience a particular processing environment. The associated wafer result variations cannot be predicted by the existing method and the existing virtual metrology model.
Therefore, what is needed is a system and method for increasing the monitoring, controlling, and/or otherwise predicting a quality and/or yield of products manufactured by a batch processing tool.